module sync_cell #(
	parameter SYNC_CYC = 2
)(
	input  clk,
	input  rst_n,
	input  in,
	output out
);
wire [SYNC_CYC :0]in_dff;
assign in_dff[0] = in;
assign out = in_dff[SYNC_CYC];

genvar i;
generate
    for(i=1; i<=SYNC_CYC; i=i+1)begin: inst_rtl
        dffr u_dffr[i](clk, rst_n, in_dff[i-1], in_dff[i]);
    end
endgenerate
endmodule